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8-, 10-, 12-, 14-bit, 175 msps txdac ? d/a converters preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2006 analog devices, inc. all rights reserved. features 0 1 pin-compatible family low power member of pin compatible txdac product family power dissipation @ 3.3 v: 21 mw @ 10 msps 24 mw @ 25 msps 30 mw @ 50 msps sleep mode: 5 mw @ 3.3 v supply voltage: 1.7 v to 3.6 v sfdr to nyquist: ad9707: 85 dbc @ 5 mhz output ad9707: 80 dbc @ 10 mhz output ad9707: 75 dbc @ 20 mhz output ad9707 snr @ 10 mhz output, 125 msps: tbd db differential current outputs: 1 ma to 5 ma data format: twos complement or straight binary on-chip 1.0 v reference cmos compatible digital interface edge-triggered latches 32-lead lfcsp package features clock input: single-ended and differential output common mode: adjustable 0 v to 1.2 v power-down mode: < 400 w @ 3.3 v (spi controllable) serial peripheral interface (spi) self-calibration 32-lead lfcsp pb-free package 28-lead tssop package features internal 500 ? load resistor internal 16k ? resistor to set full scale current output clock input: single-ended 28-lead tssop pb-free package 1 protected by u.s. patent numbers 5568145, 5689257, and 5703519 functional block diagrams figure 1. ad9707 functional block diagram (lfcsp package) figure 2. ad9707 functional block diagram (tssop package)
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 2 of 32 general description the ad9704/05/06/07 are the fourth generation family in the txdac series of high performance, cmos digital-to-analog converters (dacs). this pin compatible 8C/10C/12C/14Cbit resolution family has been optimized for low power operation while maintaining excellent dynamic performance. the ad970x family is pin compatible with the ad9748/40/42/44 family of txdac converters and is specifically optimized for the transmit signal path of communication systems. all of the devices share the same interface, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. the ad970x offers exceptional ac and dc performance while supporting update rates up to 175 msps. the ad970xs flexible power supply operating range of 1.7 v to 3.6 v and low power dissipation makes it well suited for portable and low power applications. its power dissipation can be further reduced to 15 mw with a slight degradation in performance by lowering the full-scale current output. also, a power-down mode reduces the standby power dissipation to approximately 5 mw. the ad970x-lfcsp has an optional serial peripheral interface (spi) which provides a higher level of programmability to enhance performance of the dac. an adjustable output common mode feature has also been added to the ad970x- lfcsp that allows for easy interfacing to other components that require common modes greater than 0 v. edge-triggered input latches and a 1.0 v temperature compensated band gap reference have been integrated to provide a complete monolithic dac solution. the digital inputs support 1.8 v and 3.3 v cmos logic families. product highlights 1. pin compatible: the ad970x line of txdacs is pin compatible with the ad974x txdac line. 2. low power: complete cmos dac operates on a single supply of 3.6 v down to 1.7 v, consuming 25mw (3.3v) and 10mw (1.8 v). the dac full-scale current can be reduced for lower power operation, and sleep and power-down modes are provided for low power idle periods. 3. self-calibration (foreground) enables true 14-bit inl and dnl performance. (lfcsp only) 4. data input supports twos complement or straight binary data coding. 5. high speed, single-ended and differential (lfcsp only) cmos clock input supports 175 msps conversion rate. 6. spi control offers higher level of programmability. (lfcsp package only) 7. adjustable output common mode from 0 v to 1.2 v allows for easy interfacing to other components that accept common mode levels greater than 0 v (lfcsp only). 8. on-chip voltage reference: the ad970x includes a 1.0 v temperature compensated band gap voltage reference. 9. industry-standard 28-lead tssop and 32-lead lfcsp packages.
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 3 of 32 table of contents 0 h features ................................................................................... 37 h 1 1 h 32-lead lfcsp package features................................ 38 h 1 2 h 28-lead tssop package features ............................... 39 h 1 3 h functional block diagrams...................................... 40 h 1 4 h general description ....................................................... 41 h 2 5 h product highlights ........................................................ 42 h 2 6 h ad9704/05/06/07Cspecifications .................................................. 43 h 4 7 h dc specifications (3.3 v) ........................................................... 44 h 4 8 h dynamic specifications (3.3v) .................................................. 45 h 6 9 h digital specifications (3.3v) ...................................................... 46 h 7 10 h dc specifications (1.8v) ............................................................ 47 h 8 11 h dynamic specifications (1.8v) ................................................ 48 h 10 12 h digital specifications (1.8v) .................................................... 49 h 11 13 h absolute maximum ratings......................................................... 50 h 12 14 h thermal characteristics ........................................................... 51 h 12 15 h esd caution............................................................................... 52 h 12 16 h pin configuration and function descriptions .......................... 53 h 13 17 h definitions of specifications ........................................................ 54 h 17 18 h ad9707Ctypical performance characteristics ......................... 55 h 18 19 h functional description ................................................................. 56 h 21 20 h serial peripheral interface (lfcsp only) ............................... 57 h 21 21 h spi register map ....................................................................... 58 h 23 22 h spi register descriptions ......................................................... 59 h 23 23 h reference operation ................................................................. 60 h 24 24 h reference control amplifier.................................................... 61 h 24 25 h dac transfer function ............................................................ 62 h 24 26 h analog outputs.......................................................................... 63 h 25 27 h adjustable output common mode (lfcsp only) ............... 64 h 26 28 h digital inputs ............................................................................. 65 h 26 29 h clock input................................................................................. 66 h 26 30 h dac timing............................................................................... 67 h 26 31 h power dissipation...................................................................... 68 h 27 32 h evaluation board ........................................................................... 69 h 29 33 h general description .................................................................. 70 h 29 34 h outline dimensions ...................................................................... 71 h 30 35 h ordering guide.............................................................................. 72 h 31 36 h revision history ............................................................................ 73 h 32
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 4 of 32 ad9704/05/06/07Cspecifications dc specifications (3.3 v) (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 2 ma, unless otherwise noted.) table 1. ad9707 ad9706 ad9705 ad9704 parameter min typ max min typ max min typ max min typ max unit resolution 14 bits dc accuracy 0 f 1 integral nonlinearity (inl) pre- calibration 3 0.5 0.12 tbd lsb integral nonlinea rity (inl) post- calibration 1 f 2 0.8 0.25 0.04 tbd lsb differential nonlinearity (dnl) pre- calibration 1.5 0.25 0.07 tbd lsb differential nonlinearity (dnl) post-calibration 2 0.7 0.13 0.03 tbd lsb analog output offset error -0.02 +0.02 -0.02 +0.02 -0.02 +0.02 -0.02 +0.02 % of fsr gain error (without internal reference) % of fsr gain error (with internal reference) -0.8 -0.2 +0.2 -0.8 -0.2 +0.2 -0.8 -0.2 +0.2 -0.8 -0.2 +0.2 % of fsr full-scale output current 2 f 3 1 2 5 1 2 5 1 2 5 1 2 5 ma output compliance range -1 +1.25 -1 +1.25 -1 +1.25 -1 +1.25 v output resistance 200 200 200 200 m output capacitance 5 5 5 5 pf reference output reference voltage 1.0 1.0 1.0 1.0 v reference output current 3 f 4 100 100 100 100 na reference input input compliance range 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 v reference input resistance (ext. reference) 1 1 1 1 m small signal bandwidth 0.5 0.5 0.5 0.5 mhz temperature coefficients offset drift 0 0 0 0 ppm of fsr/c gain drift (without internal reference) tbd tbd tbd tbd ppm of fsr/c gain drift (with internal reference) 70 70 70 70 ppm of fsr/c reference voltage drift 80 80 80 80 ppm/c power supply supply voltages avdd 2.5 3.3 3.6 2.5 3.3 3.6 2.5 3.3 3.6 2.5 3.3 3.6 v dvdd 2.5 3.3 3.6 2.5 3.3 3.6 2.5 3.3 3.6 2.5 3.3 3.6 v clkvdd 2.5 3.3 3.6 2.5 3.3 3.6 2.5 3.3 3.6 2.5 3.3 3.6 v analog supply current (i avdd ) 4.5 4.5 4.5 4.5 ma digital supply current (i dvdd ) 4 f 5 1.1 1.1 1.1 1.1 ma clock supply current (i clkvdd ) 1.7 1.7 1.7 1.7 ma supply current sleep mode (i avdd ) 0.4 1.0 0.4 1.0 0.4 1.0 0.4 1.0 ma supply current power-down mode 20 20 20 20 a
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 5 of 32 power dissipation 74 h 5 24 24 24 24 mw power dissipation 5 f 6 46 46 46 46 mw power supply rejection ratio avdd 6 f 7 -1 +1 -1 +1 -1 +1 -1 +1 % of fsr/v power supply rejection ratio dvdd 75 h 7 -0.04 +0.04 -0.04 +0.04 -0.04 +0.04 -0.04 +0.04 % of fsr/v operating range -40 +85 -40 +85 -40 +85 -40 +85 c 1 measured at iouta, dr iving a virtual ground. 2 calibration offered in lfcsp package only. 3 nominal full-scale current, i outfs , is 32 times the i ref current. 4 an external buffer amplifier with input bias current <100 na should be used to drive any external load. 5 measured at f clock = 25 msps and f out = 2.5 mhz. 6 measured at f clock = 175 msps and f out = 20 mhz. 7 5% power supply variation.
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 6 of 32 dynamic specifications (3.3v) (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 2 ma, differential transformer coupled output, 500 terminated, unless otherwise noted.) table 2 ad9707 ad9706 ad9705 ad9704 parameter min typ max min typ max min typ max min typ max unit dynamic performance maximum output update rate (f clock ) 175 175 175 175 msps output settling time (t st ) (to 0.1%) 7 f 1 tbd tbd tbd tbd ns output propagation delay (t pd ) tbd tbd tbd tbd ns glitch impulse tbd tbd tbd tbd pv-s output rise time (10% to 90%) 76 h 1 tbd tbd tbd tbd ns output fall time (10% to 90%) 77 h 1 tbd tbd tbd tbd ns output noise (i outfs = 2 ma) 45 tbd tbd tbd pa/hz ac linearity spurious-free dynamic range to nyquist f clock = 10 msps; f out = 1.00 mhz 82 79 80 tbd dbc f clock = 25 msps; f out = 1.00 mhz 80 79 80 tbd dbc f clock = 65 msps; f out = 5.00 mhz 80 91 88 tbd dbc f clock = 65 msps; f out = 10 mhz 80 82 79 tbd dbc f clock = 125 msps; f out = 15 mhz 80 82 79 tbd dbc f clock = 125 msps; f out = 25 mhz 79 82 77 tbd dbc f clock = 175 msps; f out = 20 mhz 78 77 76 tbd dbc f clock = 175 msps; f out = 40 mhz 75 75 76 tbd dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz tbd -89 -78 tbd dbc f clock = 50 msps; f out = 2.00 mhz tbd -85 -79 tbd dbc f clock = 65 msps; f out = 2.00 mhz tbd -85 -78 tbd dbc f clock = 125 msps; f out = 2.00 mhz tbd -87 -78 tbd dbc noise spectral density f clock = 175 msps; f out = 41.7 mhz; i outfs = 5 ma -164.1 -163.7 -157.4 tbd dbm/hz f clock = 175 msps; f out = 41.7 mhz; i outfs = 2 ma -168.3 -167.7 -167.5 tbd dbm/hz f clock = 175 msps; f out = 41.7 mhz; i outfs = 1 ma -169.8 -169.8 -169.7 tbd dbm/hz multitone power ratio (8 tones at 400 khz spacing) f clock = 78 msps; f out = 15.0 mhz to 18.2 mhz 0 dbfs output tbd tbd tbd tbd dbc - 6 dbfs output tbd tbd tbd tbd dbc -12 dbfs output tbd tbd tbd tbd dbc -18 dbfs output tbd tbd tbd tbd dbc 1 measured single-end ed into 500 ?load.
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 7 of 32 digital specifications (3.3v) (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 2 ma, unless otherwise noted.) table 3 ad9707 ad9706 ad9705 ad9704 parameter min typ max min typ max min typ max min typ max unit digital inputs 8 f 1 logic 1 voltage 2.1 3 2.1 3 2.1 3 2.1 3 v logic 0 voltage 0 0.9 0 0.9 0 0.9 0 0.9 v logic 1 current -10 +10 -10 +10 -10 +10 -10 +10 a logic 0 current +10 +10 +10 +10 a input capacitance 5 5 5 5 pf input setup time (t s ) tbd tbd tbd tbd ns input hold time (t h ) tbd tbd tbd tbd ns latch pulsewidth (t lpw ) tbd tbd tbd tbd ns clk inputs 9 f 2 input voltage range 0 3 0 3 0 3 0 3 v common-mode voltage 0.75 1.5 2.25 0.75 1.5 2.25 0.75 1.5 2.25 0.75 1.5 2.25 v differential voltage 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 v 1 includes clock pin on tssop packages and clk+ pin on lfcsp package in single-ended clock input mode. 2 applicable to clk+ and clkC inputs when configured for different ial clock input mode.
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 8 of 32 dc specifications (1.8v) (t min to t max , avdd = 1.8 v, dvdd = 1.8 v, clkvdd = 1.8 v, i outfs = 1 ma, unless otherwise noted.) table 4. ad9707 ad9706 ad9705 ad9704 parameter min typ max min typ max min typ max min typ max unit resolution 14 bits dc accuracy 1 f 1 integral nonlinearity (inl) pre- calibration 3 0.5 0.1 tbd lsb integral nonlinea rity (inl) post- calibration 2 f 2 0.8 0.3 0.05 tbd lsb differential nonlinearity (dnl) pre- calibration 1.5 0.3 0.07 tbd lsb differential nonlinearity (dnl) post-calibration 78 h 2 0.7 0.13 0.03 tbd lsb analog output offset error -0.02 +0.02 -0.02 +0.02 -0.02 +0.02 -0.02 +0.02 % of fsr gain error (without internal reference) % of fsr gain error (with internal reference) -0.8 -0.2 +0.2 -0.8 -0.2 +0.2 -0.8 -0.2 +0.2 -0.8 -0.2 +0.2 % of fsr full-scale output current 3 f 3 1 2 5 1 2 5 1 2 5 1 2 5 ma output compliance range -1 +1.25 -1 +1.25 -1 +1.25 -1 +1.25 v output resistance 200 200 200 200 m output capacitance 5 5 5 5 pf reference output reference voltage 1.0 1.0 1.0 1.0 v reference output current 4 f 4 100 100 100 100 na reference input input compliance range 0.1 1.25 0.1 1.25 0.1 1.25 0.1 1.25 v reference input resistance (ext. reference) 1 1 1 1 m small signal bandwidth 0.5 0.5 0.5 0.5 mhz temperature coefficients offset drift 0 0 0 0 ppm of fsr/c gain drift (without internal reference) tbd tbd tbd tbd ppm of fsr/c gain drift (with internal reference) 70 70 70 70 ppm of fsr/c reference voltage drift 80 80 80 80 ppm/c power supply supply voltages avdd 1.7 1.8 tbd 1.7 1.8 tbd 1.7 1.8 tbd 1.7 1.8 tbd v dvdd 1.7 1.8 tbd 1.7 1.8 tbd 1.7 1.8 tbd 1.7 1.8 tbd v clkvdd 1.7 1.8 tbd 1.7 1.8 tbd 1.7 1.8 tbd 1.7 1.8 tbd v analog supply current (i avdd ) 3.1 3.1 3.1 3.1 ma digital supply current (i dvdd ) 5 f 5 0.5 0.5 0.5 0.5 ma clock supply current (i clkvdd ) 0.7 0.7 0.7 0.7 ma 1 measured at iouta, dr iving a virtual ground. 2 calibration offered in lfcsp package only. 3 nominal full-scale current, i outfs , is 32 times the i ref current. 4 an external buffer amplifier with input bias current <100 na should be used to drive any external load. 5 measured at f clock = 25 msps and f out = 2.5 mhz.
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 9 of 32 supply current sleep mode (i avdd ) 0.3 0.3 0.3 0.3 ma supply current power-down mode 18 18 18 18 a power dissipation 79 h 5 8 8 8 8 mw power supply rejection ratio avdd 6 f 6 -1 +1 -1 +1 -1 +1 -1 +1 % of fsr/v power supply rejection ratio dvdd 80 h 6 -0.04 +0.04 -0.04 +0.04 -0.04 +0.04 -0.04 +0.04 % of fsr/v operating range -40 +85 -40 +85 -40 +85 -40 +85 c 6 5% power supply variation.
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 10 of 32 dynamic specifications (1.8v) (t min to t max , avdd = 1.8 v, dvdd = 1.8 v, clkvdd = 1.8 v, i outfs = 1 ma, differential transformer coupled output, 500 doubly terminated, unless otherwise noted.) table 5 ad9707 ad9706 ad9705 ad9704 parameter min typ max min typ max min typ max min typ max unit dynamic performance maximum output update rate (f clock ) 80 80 80 80 msps output settling time (t st ) (to 0.1%) 10 f 1 tbd tbd tbd tbd ns output propagation delay (t pd ) tbd tbd tbd tbd ns glitch impulse tbd tbd tbd tbd pv-s output rise time (10% to 90%) 81 h 1 tbd tbd tbd tbd ns output fall time (10% to 90%) 82 h 1 tbd tbd tbd tbd ns output noise (i outfs = 2 ma) 2 45 tbd tbd tbd pa/hz ac linearity spurious-free dynamic range to nyquist f clock = 10 msps; f out = 1.00 mhz 79 84 81 tbd dbc f clock = 25 msps; f out = 1.00 mhz 78 83 78 tbd dbc f clock = 25 msps; f out = 5 mhz 77 89 81 tbd dbc f clock = 65 msps; f out = 10 mhz 76 83 79 tbd dbc f clock = 65 msps; f out = 15 mhz 73 79 72 tbd dbc f clock = 80 msps; f out = 15 mhz 71 76 76 tbd dbc f clock = 80 msps; f out = 30 mhz 63 63 64 tbd dbc total harmonic distortion f clock = 10 msps; f out = 1.00 mhz tbd -83 -78 tbd dbc f clock = 25 msps; f out = 2.00 mhz tbd -87 -82 tbd dbc f clock = 45 msps; f out = 2.00 mhz tbd -86 -80 tbd dbc f clock = 65 msps; f out = 2.00 mhz tbd -86 -81 tbd dbc noise spectral density f clock = 80 msps; f out = 30 mhz; i outfs = 2 ma -167.4 -166.0 -161.2 tbd dbm/hz f clock = 80 msps; f out = 30 mhz; i outfs = 1 ma -170.1 -169.6 -166.2 tbd dbm/hz multitone power ratio (8 tones at 400 khz spacing) f clock = 40 msps; f out = 10 mhz to 13.2 mhz 0 dbfs output tbd tbd tbd tbd dbc - 6 dbfs output tbd tbd tbd tbd dbc -12 dbfs output tbd tbd tbd tbd dbc -18 dbfs output tbd tbd tbd tbd dbc 1 measured single-end ed into 500 ?load.
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 11 of 32 digital specifications (1.8v) (t min to t max , avdd = 1.8 v, dvdd = 1.8 v, clkvdd = 1.8 v, i outfs = 1 ma, unless otherwise noted.) table 6 ad9707 ad9706 ad9705 ad9704 parameter min typ max min typ max min typ max min typ max unit digital inputs 11 f 1 logic 1 voltage 1.2 1.8 1.2 1.8 1.2 1.8 1.2 1.8 v logic 0 voltage 0 0.5 0 0.5 0 0.5 0 0.5 v logic 1 current -10 +10 -10 +10 -10 +10 -10 +10 a logic 0 current +10 +10 +10 +10 a input capacitance 5 5 5 5 pf input setup time (t s ) tbd tbd tbd tbd ns input hold time (t h ) tbd tbd tbd tbd ns latch pulsewidth (t lpw ) tbd tbd tbd tbd ns clk inputs 12 f 2 input voltage range 0 1.8 0 1.8 0 1.8 0 1.8 v common-mode voltage 0.4 0.9 1.3 0.4 0.9 1.3 0.4 0.9 1.3 0.4 0.9 1.3 v differential voltage 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 v 1 includes clock pin on tssop packages and clk+ pin on lfcsp package in single-ended clock input mode. 2 applicable to clk+ and clkC inputs when configured for different ial clock input mode. figure 3. timing diagram
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 12 of 32 absolute maximum ratings table 7. parameter with respect to min max unit avdd acom -0.3 +3.9 v dvdd dcom -0.3 +3.9 v clkvdd clkcom -0.3 +3.9 v acom dcom -0.3 +0.3 v acom clkcom -0.3 +0.3 v dcom clkcom -0.3 +0.3 v avdd dvdd -3.9 +3.9 v avdd clkvdd -3.9 +3.9 v dvdd clkvdd -3.9 +3.9 v clock, sleep dcom -0.3 dvdd+0.3 v digital inputs, mode dcom -0.3 dvdd+0.3 v iouta, ioutb acom -1.0 avdd+0.3 v refio, reflo, fs adj acom -0.3 avdd+0.3 v clk+, clkC, cmode clkcom -0.3 clkvdd+0.3 v junction temperature 150 c storage temperature -65 +150 c lead temperature (10 sec) 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. thermal characteristics 7 f 1 thermal resistance 28-lead tssop ja = 67.7c/w 32-lead lfcsp ja = 32.5c/w 1 thermal impedance measurements were taken on a 4-layer board in still air, in accordance with eia/jesd51-7. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 13 of 32 pin configuration and fu nction descriptions 28-lead tssop 32-lead lfcsp figure 4. ad9707 pin configurations (tssop and lfcsp packages) table 8. ad9707 pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 27 db13 most significant data bit (msb). 2C13 28C32, 1, 2, 4C8 db12Cdb1 data bits 12C1. 14 9 db0 least significant data bit (lsb). 15 25 sleep / csb power-down control input. active high. contains active pull-down circuit; it may be left unterminated if no t used. must be driven low during spi operation. 16 n/a reflo reference ground when internal 1.0 v reference used. connect to avdd to disable internal reference. 17 23 refio reference input/output. serves as reference input when internal reference disabled. serves as 1.0 v reference output when internal reference acti vated. requires 0.1 f capacitor to acom when internal reference activated. 18 24 fs adj full-scale current output adjust. 19 n/a rset internal 16k resistor. connect to pin 18 (fsadj) to set 2 ma full-scale output curre nt; it may be left floating if not used. refer to page 21 for details. 20 22 acom analog common. 21 20 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 21 iouta dac current output. full-sca le current when all data bits are 1s. 23 n/a rload internal 500 termination re sistor. refer to page 21 for details. 24 18 avdd analog supply voltage (1.7 v C 3.6 v). n/a 19 otcm adjustable output commo n mode. refer to page 21 for details. n/a 17 pin / spi/reset selects spi mode or pin mode operation. active low for spi op eration. active high for non-spi operati on. pulse high to reset spi registers to default values. 25 16 mode / sdio selects input data format. connect to dcom for straight binary, dvdd for twos complement. when spi is enabled (lfcsp package only), this pi n acts as spi data input / output. n/a 15 cmode / sclk clock mode selection. connect to clkcom for single-ended cloc k receiver (drive clk+ and float clkC). connect to clkvdd for differential receiver. when spi is enabled, spi data clock input. 26 10, 26 dcom digital common. 27 3 dvdd digital supply voltage (1.7 v C 3.6 v) 28 n/a clock clock input. data la tched on positive edge of clock. n/a 12 clk+ differential clock input. n/a 13 clkC differential clock input. n/a 11 clkvdd clock supply voltage (1.7 v C 3.6 v). n/a 14 clkcom clock common.
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 14 of 32 28-lead tssop 32-lead lfcsp 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 28 27 26 25 24 23 22 21 db7 db6 db5 db4 db3 db2 db1 (lsb) db0 nc nc clock dvdd dcom mode avdd rload iouta ioutb acom rset fs adj refio reflo sleep db8 db9 db10 (msb) db11 ad9706 top view (not to scale) 24 fs adj 23 refio 22 acom 21 iouta db5 1 db4 2 dvdd 3 20 ioutb 19 otcm 18 avdd 17 pin (spi/reset) db3 4 db2 5 db1 6 (lsb) db0 7 nc 8 ad9706 top view (not to scale) pin 1 indicator n c 9 d c o m 1 0 c l k v d d 1 1 c l k + 1 2 c l k ? 1 3 c l k c o m 1 4 c m o d e ( s c l k ) 1 5 m o d e ( s d i o ) 1 6 3 2 d b 6 3 1 d b 7 3 0 d b 8 2 9 d b 9 2 7 d b 1 1 ( m s b ) 2 6 d c o m 2 5 s l e e p ( c s b ) 2 8 d b 1 0 figure 5. ad9706 pin configurations (tssop and lfcsp packages) table 9. ad9706 pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 27 db11 most significant data bit (msb). 2C11 28C32, 1, 2, 4C6 db10Cdb1 data bits 10C1. 12 7 db0 least significant data bit (lsb). 13, 14 8, 9 nc no connection 15 25 sleep / csb power-down control input. active high. contains active pull-down circuit; it may be left unterminated if no t used. must be driven low during spi operation. 16 n/a reflo reference ground when internal 1.0 v reference used. connect to avdd to disable internal reference. 17 23 refio reference input/output. serves as reference input when internal reference disabled. serves as 1.0 v reference output when internal reference acti vated. requires 0.1 f capacitor to acom when internal reference activated. 18 24 fs adj full-scale current output adjust. 19 n/a rset internal 16k resistor. connect to pin 18 (fsadj) to set 2 ma full-scale output curre nt; it may be left floating if not used. refer to page 21 for details. 20 22 acom analog common. 21 20 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 21 iouta dac current output. full-sca le current when all data bits are 1s. 23 n/a rload internal 500 termination re sistor. refer to page 21 for details. 24 18 avdd analog supply voltage (1.7 v C 3.6 v). n/a 19 otcm adjustable output commo n mode. refer to page 21 for details. n/a 17 pin / spi/reset selects spi mode or pin mode operation. active low for spi op eration. active high for non-spi operati on. pulse high to reset spi registers to default values. 25 16 mode / sdio selects input data format. connect to dcom for straight binary, dvdd for twos complement. when spi is enabled (lfcsp package only), this pi n acts as spi data input / output. n/a 15 cmode / sclk clock mode selection. connect to clkcom for single-ended cloc k receiver (drive clk+ and float clkC). connect to clkvdd for differential receiver. when spi is enabled, spi data clock input. 26 10, 26 dcom digital common. 27 3 dvdd digital supply voltage (1.7 v C 3.6 v) 28 n/a clock clock input. data la tched on positive edge of clock. n/a 12 clk+ differential clock input. n/a 13 clkC differential clock input. n/a 11 clkvdd clock supply voltage (1.7 v C 3.6 v). n/a 14 clkcom clock common.
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 15 of 32 28-lead tssop 32-lead lfcsp 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 28 27 26 25 24 23 22 21 db5 db4 db3 db2 db1 (lsb) db0 nc nc nc nc clock dvdd dcom mode avdd rload iouta ioutb acom rset fs adj refio reflo sleep db6 db7 db8 (msb) db9 ad9705 top view (not to scale) 24 fs adj 23 refio 22 acom 21 iouta db3 1 db2 2 dvdd 3 20 ioutb 19 otcm 18 avdd 17 pin (spi/reset) db1 4 (lsb) db0 5 nc 6 nc 7 nc 8 ad9705 top view (not to scale) pin 1 indicator n c 9 d c o m 1 0 c l k v d d 1 1 c l k + 1 2 c l k ? 1 3 c l k c o m 1 4 c m o d e ( s c l k ) 1 5 m o d e ( s d i o ) 1 6 3 2 d b 4 3 1 d b 5 3 0 d b 6 2 9 d b 7 2 7 d b 9 ( m s b ) 2 6 d c o m 2 5 s l e e p ( c s b ) 2 8 d b 8 figure 6. ad9705 pin configurations (tssop and lfcsp packages) table 10. ad9705 pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 27 db9 most significant data bit (msb). 2C9 28C32, 1C4 db8Cdb1 data bits 8C1. 10 5 db0 least significant data bit (lsb). 11C14 6C9 nc no connection 15 25 sleep / csb power-down control input. active high. contains active pull-down circuit; it may be left unterminated if no t used. must be driven low during spi operation. 16 n/a reflo reference ground when internal 1.0 v reference used. connect to avdd to disable internal reference. 17 23 refio reference input/output. serves as reference input when internal reference disabled. serves as 1.0 v reference output when internal reference acti vated. requires 0.1 f capacitor to acom when internal reference activated. 18 24 fs adj full-scale current output adjust. 19 n/a rset internal 16k resistor. connect to pin 18 (fsadj) to set 2 ma full-scale output curre nt; it may be left floating if not used. refer to page 21 for details. 20 22 acom analog common. 21 20 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 21 iouta dac current output. full-sca le current when all data bits are 1s. 23 n/a rload internal 500 termination re sistor. refer to page 21 for details. 24 18 avdd analog supply voltage (1.7 v C 3.6 v). n/a 19 otcm adjustable output commo n mode. refer to page 21 for details. n/a 17 pin / spi/reset selects spi mode or pin mode operation. active low for spi op eration. active high for non-spi operati on. pulse high to reset spi registers to default values. 25 16 mode / sdio selects input data format. connect to dcom for straight binary, dvdd for twos complement. when spi is enabled (lfcsp package only), this pi n acts as spi data input / output. n/a 15 cmode / sclk clock mode selection. connect to clkcom for single-ended cloc k receiver (drive clk+ and float clkC). connect to clkvdd for differential receiver. when spi is enabled, spi data clock input. 26 10, 26 dcom digital common. 27 3 dvdd digital supply voltage (1.7 v C 3.6 v) 28 n/a clock clock input. data la tched on positive edge of clock. n/a 12 clk+ differential clock input. n/a 13 clkC differential clock input. n/a 11 clkvdd clock supply voltage (1.7 v C 3.6 v). n/a 14 clkcom clock common.
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 16 of 32 28-lead tssop 32-lead lfcsp 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 28 27 26 25 24 23 22 21 db3 db2 db1 (lsb) db0 nc nc nc nc nc nc clock dvdd dcom mode avdd rload iouta ioutb acom rset fs adj refio reflo sleep db4 db5 db6 (msb) db7 ad9704 top view (not to scale) 24 fs adj 23 refio 22 acom 21 iouta db1 1 (lsb) db0 2 dvdd 3 20 ioutb 19 otcm 18 avdd 17 pin (spi/reset) nc 4 nc 5 nc 6 nc 7 nc 8 ad9704 top view (not to scale) pin 1 indicator n c 9 d c o m 1 0 c l k v d d 1 1 c l k + 1 2 c l k ? 1 3 c l k c o m 1 4 c m o d e ( s c l k ) 1 5 m o d e ( s d i o ) 1 6 3 2 d b 2 3 1 d b 3 3 0 d b 4 2 9 d b 5 2 7 d b 7 ( m s b ) 2 6 d c o m 2 5 s l e e p ( c s b ) 2 8 d b 6 figure 7. ad9704 pin configurations (tssop and lfcsp packages) table 11. ad9704 pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 27 db7 most significant data bit (msb). 2C7 28C32, 1 db6Cdb1 data bits 6C1. 8 2 db0 least significant data bit (lsb). 9C14 4C9 nc no connection 15 25 sleep / csb power-down control input. active high. contains active pull-down circuit; it may be left unterminated if no t used. must be driven low during spi operation. 16 n/a reflo reference ground when internal 1.0 v reference used. connect to avdd to disable internal reference. 17 23 refio reference input/output. serves as reference input when internal reference disabled. serves as 1.0 v reference output when internal reference acti vated. requires 0.1 f capacitor to acom when internal reference activated. 18 24 fs adj full-scale current output adjust. 19 n/a rset internal 16k resistor. connect to pin 18 (fsadj) to set 2 ma full-scale output curre nt; it may be left floating if not used. refer to page 21 for details. 20 22 acom analog common. 21 20 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 21 iouta dac current output. full-sca le current when all data bits are 1s. 23 n/a rload internal 500 termination re sistor. refer to page 21 for details. 24 18 avdd analog supply voltage (1.7 v C 3.6 v). n/a 19 otcm adjustable output commo n mode. refer to page 21 for details. n/a 17 pin / spi/reset selects spi mode or pin mode operation. active low for spi op eration. active high for non-spi operati on. pulse high to reset spi registers to default values. 25 16 mode / sdio selects input data format. connect to dcom for straight binary, dvdd for twos complement. when spi is enabled (lfcsp package only), this pi n acts as spi data input / output. n/a 15 cmode / sclk clock mode selection. connect to clkcom for single-ended cloc k receiver (drive clk+ and float clkC). connect to clkvdd for differential receiver. when spi is enabled, spi data clock input. 26 10, 26 dcom digital common. 27 3 dvdd digital supply voltage (1.7 v C 3.6 v) 28 n/a clock clock input. data la tched on positive edge of clock. n/a 12 clk+ differential clock input. n/a 13 clkC differential clock input. n/a 11 clkvdd clock supply voltage (1.7 v C 3.6 v). n/a 14 clkcom clock common.
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 17 of 32 definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called the offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). multitone power ratio the spurious-free dynamic range containing multiple carrier tones of equal amplitude. it is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. figure 8. basic ac characterization test set-up (lfcsp package)
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 18 of 32 ad9707Ctypical performance characteristics tbd figure 9. sfdr vs. f out tbd figure 10. sfdr vs. f out @ 25 msps 45 50 55 60 65 70 75 80 85 90 95 0 5 10 15 20 25 f out - mhz sfdr - dbc 0dbfs figure 11. sfdr vs. f out @ 65 msps 45 50 55 60 65 70 75 80 85 90 95 0 102030405060 f out - mhz sfdr - dbc 0dbfs -6dbfs figure 12. sfdr vs. f out @ 175 msps tbd figure 13. sfdr vs. f out and i outfs @ 65 msps tbd figure 14. single-tone sfdr vs. a out @ f out =f clock /11 tbd figure 15. single-tone sfdr vs. a out @ f out =f clock /5 tbd figure 16. snr vs. f clock and i outfs @ f out =5 mhz and 0 dbfs
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 19 of 32 tbd figure 17. dual-tone imd vs. a out @ f out =f clock /7 tbd figure 18. typical inl tbd figure 19. typical dnl tbd figure 20. sfdr vs. temperature @ 125 msps tbd figure 21. single-tone sfdr tbd figure 22. dual-tone sfdr tbd figure 23. four-tone sfdr
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 20 of 32 figure 24. simplified block diagram (lfcsp package)
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 21 of 32 functional description 83 h figure 24 shows a simplified block diagram of the ad970x. the ad970x consists of a dac, digital control logic, and full- scale output current control. the dac contains a pmos current source array capable of providing a nominal full-scale current (i outfs ) of 2 ma and a maximum of 5 ma. the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are binary weighted fractions of the middle bits current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dacs high output impedance (i.e., >200m ? ). all of these current sources are switched to one or the other of the two output nodes (i.e., iouta or ioutb) via pmos differential current switches. the switches are based on the architecture that was pioneered in the ad9764 family, with further refinements to reduce distortion contributed by the switching transient. this switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the ad970x have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 1.7 v to 3.6 v range. the digital section, which is capable of operating at a rate of up to 175 msps, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.0 v band gap voltage reference, and a reference control amplifier. the dac full-scale output current is regulated by the reference control amplifier and can be set from 1 ma to 5 ma via an external resistor, r set , connected to the full-scale adjust (fs adj) pin. the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the reference current i ref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is 32 times i ref . the ad970x-lfcsp provides the option of setting the output common mode to a value other than acom via the output common mode (otcm) pin. this option allows the user to directly interface the output of the ad970x to components that require common mode levels greater than 0 v. serial peripheral interface (lfcsp only) the ad970x serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi? and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad970x. single or multiple byte transfers are supported, as well as msb first or lsb first transfer formats. the ad970xs serial interface port is configured as a single pin i/o. general operation of the serial interface there are two phases to a communication cycle with the ad970x. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad970x, coincident with the first eight sclk rising edges. the instruction byte provides the ad970x serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad970x. a logic high on pin 17 (spi res/pin), followed by a logic low, will reset the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the spi port. if the spi port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad970x and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. using one multibyte transfer is the preferred method. single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the information shown in table 9. msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 table 12. spi instruction byte r/w , bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. n1, n0, bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table 10.
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 22 of 32 a4, a3, a2, a1, a0, bits 4, 3, 2, 1, 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad970x based on the datadir bit (reg00, bit 6). n1 n1 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes table 13. byte transfer count serial interface port pin descriptions sclkserial clock. the serial clock pin is used to synchronize data to and from the ad970x and to run the internal state machines. sclks maximum frequency is 20 mhz. all data input to the ad970x is registered on the rising edge of sclk. all data is driven out of the ad970x on the falling edge of sclk. csbchip select. active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the sdio pin will go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdioserial data i/o. this pin is used as a bidirectional data line to transmit and receive data. msb/lsb transfers the ad970x serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by register bit datadir (reg00, bit 6). the default is msb first (datadir = 0). when datadir = 0 (msb first) the instruction and data bytes must be written from most significant bit to least significant bit. multibyte data transfers in msb first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow in order from high address to low address. in msb first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. when datadir = 1 (lsb first) the instruction and data bytes must be written from least significant bit to most significant bit. multibyte data transfers in lsb first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. the ad970x serial port controller data address will decrement from the data address written toward 0x00 for multibyte i/o operations if the msb first mode is active. the serial port controller address will increment from the data address written toward 0x1f for multibyte i/o operations if the lsb first mode is active. notes on serial port operation the ad970x serial port configuration is controlled by reg00, bit 7. it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur during the middle of communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the software reset, reset (reg00, bit 5). all registers are set to their default values except reg00 which remains unchanged. use of only single byte transfers when changing serial port configurations or initiating a software reset is recommended to prevent unexpected device behavior. tbd figure 25. serial register interface timing msb first tbd figure 26. serial register interface timing lsb first tbd figure 27. timing diagram for spi register write tbd figure 28. timing diagram for spi register read
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 23 of 32 spi register map table 14 address bit 7bit 6bit 5bit 4bit 3 bit 2bit 1bit 0 spi ctl 00 sdiodir datadir swrst lngins pdn sleep clkoff exref data 02 datafmt dclkpol lowskew clkdiff calclk calmem 0e calmem[1] calmem[0] divsel[3] divsel[2] divsel[1] divsel[0] memrdwr 0f calstat calen smemwr smemrd uncal memaddr 10 memaddr[5] memaddr[4] memaddr[3] memaddr[2] memaddr[1] memaddr[0] memdata 11 memdata[5] memdata[4] memdata[3] memdata[2] memdata[1] memdata[0] anaetst 17 prelds1 cdaoff one of spi register descriptions table 15 spi cntl (00) bit direction (i/o) default description sdiodir 7 i 1 1: sdio pin hardwired for input or output during data transfer (3-wire interface) 0: serial data uses msb first format 1: serial data uses lsb first format 0: software reset not enabled (running) 1: default all serial register bits, except address 00h 0: use 1 byte premable (5 address bits) 1: use 2 byte preamble (13 adress bits) pdn 3 i 0 1: all analog and digital circuitry off, except serial interface sleep 2 i 0 1: dac output current off clkoff 1 i 0 1: clock off 0: internal bandgap reference 1: external reference data (02) bit direction (i/o) default description 0: unsigned binary input data format 1: 2's complement input data format 0: data latched on dataclk rising edge 1: data latched on dataclk falling edge 0: low skew mode disabled 1: low skew mode enabled 0: single-ended clock input 1: differential clock input 0: calibration clock disabled 1: calibration clock enabled calmem (0e) bit direction (i/o) default description calibration memory 00: uncalibrated 01: self calibration 11: user input calibration clock divide ratio from channel data rate 0000: / 256 0001: / 128 : 1110: / 2 1111: / 1 memrdwr (0f) bit direction (i/o) default description 0: calibration cycle not complete 1: calibration cycle complete calen 6 i 0 1: calibration in progress smemwr 3 i 0 1: write static memory data from external port smemrd 2 i 0 1: read static memory to external port uncal 0 i 0 1: use uncalibrated memaddr (10) bit direction (i/o) default description memaddr[5:0] [5:0] i/o 00000 address of static memory to be accessed memdata (11) bit direction (i/o) default description memdata[5:0] [5:0] i/o 11111 data for static memory access anaetst (17) bit direction (i/o) default description 0: pre-load calibration reference specified by user 1: pre-load calibration reference of 32 prelds1 3 i 0 o00 exref datadir swrst lngins 0 6 5 4 i i i i 0 0 0 0 datafmt 7i 0 0 i 2 dclkpol 4 i 0 lowskew 3 i 0 clkdiff calstat 7 o 0 0 divsel[2:0] calclk 0 i [3:0] i 0000 calmem[5:4] [5:4]
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 24 of 32 reference operation the ad970x contains an internal 1.0 v band gap reference. the internal reference can be disabled in both packages. to disable the reference in the 32-lead lfcsp package, a logic 1 must be written to reg00, bit 0 (exref) in the spi. in the 28-lead tssop package, the reference can be disabled by raising reflo to avdd. in both packages, the reference can also be overridden by an external reference with no effect on performance. refio serves as either an input or an output depending on whether the internal or an external reference is used. table 13 summarizes the reference operation for the lfcsp and tssop package options. reference mode refio pin lfcsp tssop internal connect 0.1 f capacitor reg00, bit 0 = 0 (default) reflo = acom external a pply external reference reg00, bit 0 = 1 reflo = avdd table 16. reference operation (tssop and lfcsp packages) to use the internal reference, simply decouple the refio pin to acom with a 0.1 f capacitor and enable the internal reference. to enable the internal reference in the 28-lead tssop package, connect reflo to acom via a resistance less than 5 ? . in the lfcsp package, a logic 0 must be written to reg00, bit 0 in the spi. (note that this is the default configuration for the lfcsp package.) the internal reference voltage will be present at refio. if the voltage at refio is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 na should be used. an example of the use of the internal reference is shown in 84 h figure 29. tbd figure 29. internal reference configuration an external reference can be applied to refio, as shown in 85 h tbd figure 30. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of refio minimizes any loading of the external reference. tbd figure 30. external reference configuration reference control amplifier the ad970x contains a control amplifier that is used to regulate the full-scale output current, i outfs . the control amplifier is configured as a v-i converter, as shown in 86 h figure 29, so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 87 h (4). i ref is copied to the segmented current sources with the proper scale factor to set ioutfs, as stated in equation 88 h (3). the control amplifier allows a 5:1 adjustment span of i outfs from 1 ma to 5 ma by setting i ref between 31.25 a and 156.25 a (r set between 6.4 k ? and 32 k ? ) . the wide adjustment span of i outfs provides several benefits. the first relates directly to the power dissipation of the ad970x, which is proportional to i outfs (refer to the power dissipation section). the second benefit relates to the ability to adjust the output over a 14 db range, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 500 khz and can be used for low frequency small signal multiplying applications. dac transfer function the ad970x provides complementary current outputs, iouta and ioutb. iouta provides a near fullscale current output, i outfs , when all bits are high (i.e., dac code = 16383), while ioutb, the complementary output, provides no current. the current output appearing at iouta and ioutb is a function of both the input code and i outfs and can be expressed as ( ) outfs i code dac iouta = 16384 / (1) ( ) outfs i code dac ioutb ? = 16384 / 16383 (2) where dac code = 0 to 16383 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio , and external resistor, r set . it can be expressed as re f outfs i i = 32 (3) where set refio re f r v i / = (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, iouta
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 25 of 32 and ioutb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. the single-ended voltage output appearing at the iouta and ioutb nodes is simply load outa r iouta v = (5) load outb r ioutb v = (6) note: to achieve the maximum output compliance of 1 v at the nominal 2 ma output current, r load must be set to 500 ? . also note that the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance the 28-lead tssop package option contains two internal resistors (r set = 16 k ? and r load = 500 ? ) that can be used to configure the ad970x with a reduced number of external resistors. connecting the rset pin to the fsadj pin sets the full scale output current to 2 ma without the need for an external r set resistor. connecting the rload pin to iouta allows the user to generate a single-ended output driving into a 500 ? load without the need for an external r load resistor. () load dif f r ioutb iouta v ? = (7) substituting the values of iouta, ioutb, i ref , and v diff can be expressed as () {} () load set refio diff r r v code dac v ? = / 32 16384 / 16383 2 (8) equations 89 h (7) and 90 h (8) highlight some of the advantages of operating the ad970x differentially. first, the differential operation helps cancel common-mode error sources associated with iouta and ioutb, such as noise, distortion, and dc offsets. second, the differential code dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (v outa and v outb ) or differential output (v diff ) of the ad970x can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship, as shown in equation 91 h (8). analog outputs the complementary current outputs in each dac, iouta, and ioutb may be configured for single-ended or differential operation. iouta and ioutb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equations 92 h (5) through 93 h (8). the differential voltage, v diff , existing between v outa and v outb , can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. the ac performance of the ad970x is optimum and specified using a differential transformer-coupled output in which the voltage swing at iouta and ioutb is limited to 0.5 v. the distortion and noise performance of the ad970x can be enhanced when it is configured for differential operation. the common-mode error sources of both iouta and ioutb can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. this is due to the first order cancellation of various dynamic common- mode distortion mechanisms, digital feedthrough, and noise. performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). since the output currents of iouta and ioutb are complementary, they become additive when processed differentially. as mentioned above, if the ad970x is being used at its nominal operating point of 2 ma output current, and 1 v output swing is desired, r load must be set to 500 ? . a properly selected transformer will allow the ad970x to provide the required power and voltage levels to different loads. the output impedance of iouta and ioutb is determined by the equivalent parallel combination of the pmos switches associated with the current sources and is typically 200 m in parallel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa and v outb ) due to the nature of a pmos device. as a result, maintaining iouta and/or ioutb at a virtual ground via an i-v op amp configuration will result in the optimum dc linearity. note that the inl/dnl specifications for the ad970x are measured with iouta maintained at a virtual ground via an op amp. iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of C1 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 26 of 32 breakdown of the output stage and affect the reliability of the ad970x. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.2 v for an i outfs = 2 ma to 1 v for an i outfs = 1 ma. the optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at iouta and ioutb does not exceed 0.5 v. adjustable output common mode (lfcsp only) the 32-lead lfcsp package option provides the ability to set the output common mode to a value other than acom via pin 19 (otcm). this option allows the user to directly interface the output of the ad970x to components that require common mode levels other than 0 v. the otcm pin contains some amount of data switching current and thus should be actively driven to the desired voltage level when not tied directly to acom. optium performance is achieved when the voltage on otcm is equal to the center of the output swing on iouta and ioutb. note that setting otcm to a voltage greater than acom allows the peak of the output signal to be closer to the positive supply rail. to prevent distortion in the output signal due to limited available headroom, the supply voltage, common mode level must be chosen such that the following expression is satisfied: v v a otcm vdd 0 . 2 > ? (10) digital inputs the ad970x digital section consists of 14 input bit channels and a clock input. the 14-bit parallel data inputs can follow standard positive binary or twos complement coding, where db13 is the most significant bit (msb) and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. figure 31. equivalent digital input the digital interface is implemented using an edge-triggered master/slave latch. the dac output updates on the rising edge of the clock and is designed to support a clock rate as high as 175 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. clock input tssop package the 28-lead tssop package option has a single-ended clock input (clock) that must be driven to rail-to-rail cmos levels. the quality of the dac output is directly related to the clock quality and jitter is a key concern. any noise or jitter in the clock will translate directly into the dac output. optimal performance will be achieved if the clock input has a sharp rising edge, since the dac latches are positive edge triggered. lfcsp package a configurable clock input is available in the 32-lead lfcsp package, which allows for a single-ended and a differential clock mode. the mode selection can be controlled either by the cmode pin if the spi is disabled or through spi reg02, bit 2 (clkdiff) if the spi is enabled. connecting cmode to clkcom selects the single-ended clock input. in this mode, the clk+ input is driven with rail-to-rail swings and the clkC input is left floating. if cmode is connected to clkvdd, the differential receiver mode is selected. in this mode, both inputs are high impedance. 94 h table 17 summarizes the clock mode control for the lfcsp version of the ad970x. there is no significant performance difference between the clock input modes. spi disabled spi enabled cmode pin reg02, bit 2 clock input mode clkcom 0 single-ended clkvdd 1 differential table 17. clock mode selection (lfcsp package) the single-ended clock in the lfcsp package has the same operating requirements as the tssop single-ended clock. please refer to the section describing the tssop single-ended clock input for details on operating requirements. in the differential input mode, the clock input functions as a high impedance differential pair. the common-mode level of the clk+ and clkC inputs can vary from 0.75 v to 2.25 v, and the differential voltage can be as low as 0.5 v p-p. this mode can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally. dac timing input clock and data timing relationship dynamic performance in a dac is dependent on the relationship between the position of the clock edges and the time at which the input data changes. the ad970x is rising-
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 27 of 32 edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. in general, the goal when applying the ad970x is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. 95 h figure 32 shows the relationship of sfdr to clock placement with different sample rates. note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. tbd figure 32. sfdr vs. clock placement @ f out =20 mhz and 50 mhz power dissipation the power dissipation, p d , of the ad970x is dependent on several factors that include: ? the power supply voltages (avdd, cvdd, and dvdd) ? the full-scale current output i outfs ? the update rate f clock ? the reconstructed digital input waveform the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i av dd is directly proportional to i outfs , as shown in 96 h figure 33, and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input waveform, f clock , and digital supply dvdd. 97 h figure 34 shows i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 3.3 v. i clkvdd is directly proportional to f clock , and is higher for differential clock operation than single-ended operation. this difference in clock current is due primarily to the differential clock receiver which is disabled in single-ended clock mode. 0 1 2 3 4 5 6 7 8 12345 i outfs (ma) i avdd (ma) figure 33. i avdd vs i outfs 0 1 2 3 4 5 6 7 8 9 10 0.01 0.1 1 f out /f clock i clkvdd (ma) figure 34. i dvdd vs f out /f clk ratio @ dvdd=3.3 v 0 1 2 3 4 5 0 50 100 150 200 f clk (m sps) i clkvdd (ma) figure 35. i clkvdd vs. f clock (differential clock mode) sleep and power-down mode operation the ad970x has a sleep mode that turns off the output current and reduces the total supply current to less than 3.5 ma over the specified supply range of 1.7 v to 3.6 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 x avdd. this digital input also contains an active pulldown circuit that ensures that the ad970x remains enabled if this input is left disconnected. the ad970x takes less than 50 ns to power down and approximately 5 s to power back up. lfcsp package the 32-lead lfcsp package option offers three power-down functions that can be controlled through the spi, if enabled. these power-down modes reduce the power dissipation to as little as 120 a. the power-down functions are controlled through spi reg00, bits 1C3. table 15 below summarizes the power-down functions of the ad 970x that can be controlled through the spi. the power-down mode can be enabled by writing a logic level 1 to the corresponding bit in register 00. power down mode bit (reg00) functional description clock off 1 turn off clock sleep 2 turn off output current diff se 175 msps 125 msps 75 msps 25 msps 10 msps
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 28 of 32 power down 3 turn off clock, output current and internal voltage reference table 18. power-down mode selection (lfcsp package)
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 29 of 32 evaluation board general description the txdac family evaluation boards allow for easy setup and testing of any txdac product in the tssop and lfcsp packages. careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the ad970x easily and effectively in any application where low power, high resolution, high speed conversion is required. this board allows the user the flexibility to operate the ad970x in various configurations. possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. the digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. provisions are also made to operate the ad970x with either the internal or external reference or to exercise the power-down feature.
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 30 of 32 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 36. 32-lead lead frame chip scale package [lfcsp_vq] 5mm 5mm, very thin quad (cp-32-2) dimensions shown in millimeters compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 37. 28-lead thin shrink small outline package [tssop (ru-28) dimensions shown in millimeters
preliminary technical data ad9704/ad9705/ad9706/ad9707 rev. prc | page 31 of 32 ordering guide model temperature range package description package options aD9704BRUZ -40c to +85c 28-lead tssop ru-28 aD9704BRUZrl7 -40c to +85c 28-lead tssop ru-28 ad9704bcpz -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9704bcpzrl7 -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9704bcp-pcb evaluation board (lfcsp) ad9704bru-pcb evaluation board (tssop) ad9705bruz -40c to +85c 28-lead tssop ru-28 ad9705bruzrl7 -40c to +85c 28-lead tssop ru-28 ad9705bcpz -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9705bcpzrl7 -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9705bcp-pcb evaluation board (lfcsp) ad9705bru-pcb evaluation board (tssop) ad9706bruz -40c to +85c 28-lead tssop ru-28 ad9706bruzrl7 -40c to +85c 28-lead tssop ru-28 ad9706bcpz -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9706bcpzrl7 -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9706bcp-pcb evaluation board (lfcsp) ad9706bru-pcb evaluation board (tssop) ad9707bruz -40c to +85c 28-lead tssop ru-28 ad9707bruzrl7 -40c to +85c 28-lead tssop ru-28 ad9707bcpz -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9707bcpzrl7 -40c to +85c 32-lead lfcsp_vq cp-32-2 ad9707bcp-pcb evaluation board (lfcsp) ad9707bru-pcb evaluation board (tssop)
ad9704/ad9705/ad9706/ad9707 preliminary technical data rev. prc | page 32 of 32 revision history location page 1/06?data sheet changed from rev. prb to rev. prc. added ad9704/05/06 generics an d related data universal 7/05?data sheet changed from rev. a to rev. prb. universal 4/05?data sheet changed from rev. 0 to rev. a. added 28-lead tssop package universal ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are t he propert y of th eir r espective companie s. printed in the u.s.a.

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